The semiconductor packaging game is getting dicey, and everyone’s looking for an angle. We’re not talking about slapping a sticker on a chip here; this is the high-stakes, ultra-precise world of advanced packaging, where microscopic precision dictates the performance of everything from your smartphone to the AI server farms chewing through the world’s data. And according to DIGITIMES senior analyst Luke Lin, the latest dust-up involves MediaTek, Intel, and TSMC’s crown jewel, its CoWoS packaging technology.
Look, when Warren Buffett throws billions at a company, it’s not usually for kicks. Lin points out that Buffett’s massive Apple investment isn’t just a stock pick; it’s a bet on Tim Cook’s steady hand, transforming Apple into Berkshire Hathaway’s biggest asset. Cook, for all the hand-wringing about a lack of flashy new products, has apparently mastered the art of market-value management. Who knew steady growth could be so… profitable?
But that’s not the headline that’s got the industry buzzing. The real drama is unfolding in the foundries. MediaTek recently brought on Douglas Yu, the guy they’re calling the “father of CoWoS,” a pretty big deal considering CoWoS is TSMC’s gold standard in advanced packaging. Naturally, whispers started that MediaTek was doing this to help Google’s next-gen TPU chip hop onto Intel’s EMIB-T packaging. This is serious business, implying MediaTek might be poaching talent to help a rival chipmaker – and implicitly, a rival to TSMC, MediaTek’s long-time partner.
MediaTek, predictably, has pushed back. They’ve issued a statement saying Yu’s role is strictly about improving their own advanced packaging work with TSMC. No Intel shenanigans here, folks. Just business as usual, moving their own chips forward. Uh-huh.
The Math of Making Chips
Let’s talk numbers, because that’s where the real story lies. Lin drops a bomb about the economics of yield. Intel’s EMIB-T packaging, he claims, has a 90% yield. Sounds good, right? Almost perfect. Wrong. For the kind of high-end, complex chips we’re talking about – AI accelerators, for instance, which are basically incredibly expensive logic wafers glued to equally pricey HBM memory – 90% is a recipe for disaster. That means one in ten units just doesn’t make it. Think about the cost of those initial wafers alone.
Compare that to TSMC’s CoWoS-L, which Lin predicts will be hitting over 98% yield by 2026. A nearly perfect output. The math is simple: if Intel messes up, and these companies are losing entire high-value wafer stacks that they likely bought from TSMC, the packaging fees Intel would collect are peanuts compared to the losses incurred. The more packaging Intel does, the more it could actually lose if those yields don’t skyrocket.
Lin said Google remains undecided on orders for its second-generation TPU and has not fully shifted to Intel, partly because Intel’s technology maturity and yield have yet to match TSMC’s.
So, it’s no wonder Google is playing coy about its next TPU orders. They’re not going to jump ship based on promises when the established player, TSMC, is delivering the goods with rock-solid yields.
TSMC’s Price Hike Power Play
And then there’s TSMC itself. You think they’re just going to sit back and let everyone undercut them? Not a chance. Lin brings up a juicy tidbit: Cook himself apparently complained that limited TSMC advanced-node capacity hampered iPhone sales. This isn’t a bug; it’s a feature of TSMC’s runaway success. Building these cutting-edge foundries takes years, and right now, their capacity is already stretched thinner than a starving supermodel – utilization is over 100%. That’s not a typo.
As TSMC’s use grows, so will its prices. Lin forecasts a significant jump in foundry prices for new processes in 2027. They’re done being the polite supplier. Expect them to start charging what their incredibly scarce, highly advanced technology is actually worth. The era of bargain-basement chip manufacturing is over, my friends. Welcome to the era of premium silicon.
