A 300mm silicon wafer costs a foundry like TSMC between $100 and $200 in raw material form. After being processed through hundreds of manufacturing steps over two to three months, that same wafer can produce chips worth $50,000 to $200,000 or more, depending on the process node, die size, and yield. Understanding this transformation, the economics of wafer manufacturing, is essential for anyone seeking to comprehend why chips cost what they do, why certain companies are more profitable than others, and why process node decisions carry such enormous financial consequences.
From Sand to Silicon Wafer
The journey begins with high-purity silicon, refined from quartz sand through a complex chemical process. A single crystal of silicon is grown using the Czochralski method, in which a seed crystal is slowly pulled from a vat of molten silicon, forming a cylindrical ingot weighing up to 100 kilograms. This ingot is then sliced into thin wafers, polished to an atomic-level smoothness, and cleaned to remove any contamination.
The industry standard wafer diameter is 300mm (12 inches), which has been the norm since the early 2000s. Larger wafers are more economical because they produce more chips per wafer while sharing the same fixed processing costs. The semiconductor industry has discussed transitioning to 450mm wafers for years, but the enormous capital required for new equipment has repeatedly delayed this transition. Most industry observers now believe 300mm will remain the standard for at least another decade.
A bare 300mm silicon wafer costs roughly $100 to $200. The finished wafer, after all manufacturing steps, can cost anywhere from $2,000 for a mature process node like 180nm to over $20,000 for a leading-edge process like TSMC's N3 (3nm). The difference is entirely attributable to the complexity and cost of the fabrication process.
Wafer Processing Costs by Node
The cost of processing a wafer increases substantially with each new process node. This increase reflects the growing number of process steps, the use of more expensive equipment (particularly EUV lithography), and the tighter process control required for smaller features.
At a mature node like 28nm, a wafer requires approximately 400 to 500 processing steps and costs roughly $3,000 to $4,000 to process. At 7nm, the step count increases to 800 to 1,000, and the wafer cost rises to $10,000 to $12,000. At 3nm, wafer costs are estimated at $18,000 to $20,000, with step counts exceeding 1,200. These costs include depreciation of equipment, chemicals, gases, cleanroom operation, and labor, but not the design costs borne by the chip company.
- 28nm wafer cost: approximately $3,000-$4,000
- 7nm wafer cost: approximately $10,000-$12,000
- 5nm wafer cost: approximately $14,000-$17,000
- 3nm wafer cost: approximately $18,000-$20,000
Despite these rising per-wafer costs, the cost per transistor has continued to decrease at leading-edge nodes, though the rate of decrease has slowed. A 3nm process packs far more transistors per square millimeter than a 7nm process, so even though the wafer costs more, each transistor is cheaper. This dynamic, the ongoing reduction in cost per transistor, is the economic engine that has driven Moore's Law for decades.
Die Size and Chips Per Wafer
The number of chips (dies) that can be cut from a single wafer depends on the die size and the wafer diameter. A 300mm wafer has a usable area of approximately 70,000 square millimeters. A small microcontroller die measuring 10mm by 10mm (100 square millimeters) yields roughly 600 good dies per wafer. A large data center GPU measuring 800 square millimeters yields only about 70 dies per wafer.
This relationship between die size and chip count has profound economic implications. A small die benefits from high volume production, as hundreds of chips share the same wafer cost. A large die concentrates more cost into fewer chips, and any manufacturing defect is more likely to affect it. This is one reason why the largest chips, like NVIDIA's flagship GPUs, command premium prices.
The edge of the wafer also plays a role. Circular wafers cannot tile perfectly with rectangular dies, and chips near the edge may be incomplete or have reduced quality. The "edge loss" is proportional to the chip's perimeter relative to the wafer's circumference. Larger dies suffer greater proportional edge losses than smaller ones.
Yield: The Critical Variable
Yield, the percentage of manufactured dies that function correctly, is the most important variable in wafer economics. A brand-new process might start with yields below 30 percent, meaning more than two-thirds of dies must be discarded. Mature processes at established nodes can achieve yields above 95 percent.
Yield depends on two main factors: the density of defects on the wafer and the size of the die. Random particle contamination and process variations create defects scattered across the wafer. The probability that at least one defect falls within a die increases with die area. This relationship follows a statistical model first described by Murphy's law of yields: larger dies have disproportionately lower yields than smaller dies on the same wafer.
For a hypothetical defect density of 0.1 defects per square centimeter, a 100mm-squared die would have a yield of approximately 90 percent. An 800mm-squared die on the same wafer would yield only about 45 percent. This is why NVIDIA's H100 GPU, with its massive die, is so expensive to manufacture. Roughly half the dies on each wafer are non-functional, and the cost of those failed dies must be absorbed by the working ones.
Yield Improvement Strategies
Chip designers and foundries employ several strategies to improve effective yield. Redundancy is common in memory chips, which include spare rows and columns that can replace defective ones during testing. Logic chips increasingly use similar techniques, with redundant compute units that can be disabled if defective.
Chiplet architectures represent a more radical approach. Instead of building one massive die, companies like AMD split their designs into multiple smaller chiplets connected through advanced packaging. Each chiplet has a higher yield due to its smaller size, and a defect in one chiplet does not waste the silicon area of the others. AMD's Ryzen processors use this approach, combining multiple CPU chiplets with a separate I/O die.
The Complete Cost Picture
To calculate the cost of a single finished chip, one must account for wafer cost, yield, packaging, and testing. Consider a hypothetical chip with a 200mm-squared die fabricated on a 5nm process.
A 300mm wafer at 5nm costs approximately $16,000. The wafer yields about 300 potential die positions. At 80 percent yield, 240 dies are functional. The wafer cost per good die is therefore $16,000 divided by 240, or roughly $67. Adding packaging costs of $10 to $50 per chip (depending on complexity), testing costs of $2 to $10, and a share of mask amortization, the total manufacturing cost per chip might be $90 to $130.
Compare this with a large 800mm-squared AI accelerator die on the same process. The wafer yields only about 70 positions, and at 50 percent yield, only 35 good dies are produced per wafer. The wafer cost per good die jumps to $457. With more expensive advanced packaging, the total manufacturing cost per chip might be $600 to $800, before any markup for profit.
These manufacturing costs represent only a fraction of the chip's final selling price. Design amortization, software development, marketing, sales, and profit margins all add to the price the customer pays. NVIDIA's H100 GPU sells for $25,000 to $40,000 despite a manufacturing cost that is likely a small fraction of that price. The premium reflects the enormous R&D investment, the value of the CUDA ecosystem, and the currently insatiable demand for AI compute.
Understanding wafer economics illuminates why the semiconductor industry behaves the way it does: why process technology leadership matters so much, why die size decisions are agonized over, why yield improvement is a never-ending pursuit, and why the largest chips carry the most staggering price tags.
