Every modern electronic device, from smartphones to data center servers, relies on semiconductor chips manufactured through one of the most complex industrial processes ever devised. Semiconductor fabrication, commonly called chip fab, transforms ordinary silicon into billions of transistors packed onto a single die. Understanding this process reveals why only a handful of companies in the world can produce leading-edge chips and why a single fabrication facility costs upward of $20 billion to build.
Starting with Silicon: Wafer Preparation
The journey begins with silicon dioxide, better known as sand. However, the silicon used in chip manufacturing must be extraordinarily pure, reaching 99.9999999% purity, often referred to as nine-nines purity. Raw silicon is refined through the Czochralski process, where a seed crystal is dipped into molten silicon and slowly pulled upward while rotating, forming a cylindrical ingot that can weigh over 100 kilograms.
This ingot is then sliced into thin wafers, typically 300mm (about 12 inches) in diameter for modern fabs. Each wafer is polished to an atomically flat surface, because even nanometer-scale imperfections would ruin the circuits built on top. The polished wafers are the blank canvases on which chips are created.
Photolithography: Printing the Circuit Pattern
Photolithography is the heart of semiconductor fabrication. It works much like printing a photograph, but at an almost unimaginably small scale. The wafer is first coated with a light-sensitive material called photoresist. A mask, which contains the circuit pattern, is then positioned above the wafer, and ultraviolet light is projected through the mask onto the photoresist.
Where the light hits, the photoresist undergoes a chemical change. In positive-tone resist, exposed areas become soluble and are washed away; in negative-tone resist, exposed areas harden. This leaves behind a precise pattern on the wafer surface. For leading-edge chips at 5nm and below, extreme ultraviolet (EUV) lithography uses light with a wavelength of just 13.5 nanometers, requiring mirrors rather than lenses and a near-vacuum environment.
Each chip requires dozens of lithography steps, one for each layer of the circuit. Alignment between layers must be accurate to within a fraction of a nanometer, a feat that requires laser interferometers and vibration-isolated equipment.
Etching and Deposition: Building Layer by Layer
After photolithography defines a pattern, the next step is to transfer that pattern into the underlying material. Etching removes material from areas not protected by the photoresist. Dry etching, using reactive ion plasma, is preferred for advanced nodes because it produces vertical sidewalls and precise feature control. Wet etching, using chemical solutions, is still used for less critical layers.
Between etching steps, new materials are deposited onto the wafer. Chemical vapor deposition (CVD) and physical vapor deposition (PVD) are used to add thin films of silicon dioxide, silicon nitride, metals, and other materials. Atomic layer deposition (ALD) deposits material one atomic layer at a time, giving unparalleled thickness control at the sub-nanometer level.
Doping: Creating Electrical Properties
Pure silicon is a poor conductor of electricity. To make transistors, specific regions of the silicon must be doped, meaning tiny amounts of other elements are introduced to change its electrical properties. Adding phosphorus or arsenic creates n-type silicon with extra electrons, while adding boron creates p-type silicon with electron vacancies called holes.
Ion implantation is the primary doping method in modern fabs. Atoms of the dopant element are ionized, accelerated in an electric field, and shot into the silicon surface. The depth and concentration of the implant are precisely controlled by adjusting the beam energy and dose. After implantation, the wafer is annealed at high temperature to repair crystal damage and activate the dopants.
Metallization: Wiring It All Together
Transistors are useless unless they are connected to each other. Metallization creates the interconnect layers, an intricate network of copper wires and insulating layers stacked above the transistors. Modern chips have 10 to 15 metal layers, with the finest wires at the bottom (near the transistors) and progressively thicker wires at the top for power distribution and signals that must travel longer distances.
Copper replaced aluminum as the interconnect metal in the late 1990s because of its lower resistance. The damascene process is used: trenches are etched into the insulating layer, filled with copper through electroplating, and then polished flat using chemical mechanical planarization (CMP). At advanced nodes, the resistance of these tiny copper wires becomes a significant performance bottleneck, driving research into alternative materials like ruthenium and cobalt.
Testing, Dicing, and Packaging
Once all layers are complete, each die on the wafer is tested using probe cards that make electrical contact with test pads. Dies that fail are marked and discarded. The wafer is then cut into individual dies using a diamond saw or laser. Good dies are mounted into packages that provide physical protection, electrical connections (pins or solder bumps), and thermal management.
Packaging has become increasingly sophisticated. Advanced packages can stack multiple dies vertically (3D stacking), place them side by side on a silicon interposer (2.5D), or integrate chiplets from different process nodes into a single package. This final step determines how the chip interfaces with the rest of the system and plays a critical role in overall performance.
The Scale of the Challenge
A modern fab runs 24 hours a day, 7 days a week, processing wafers through 700 to 1,400 individual steps over a period of two to three months. The cleanroom environment must be thousands of times cleaner than a hospital operating room, with fewer than 10 particles per cubic meter of air. A single speck of dust can ruin an entire chip.
The capital intensity is staggering. TSMC's newest fabs in Arizona cost over $40 billion, and a single EUV lithography machine from ASML costs approximately $350 million. These economics explain why semiconductor fabrication has consolidated into just three companies capable of producing chips at the most advanced nodes: TSMC, Samsung, and Intel.
Despite these challenges, the semiconductor industry continues to push the boundaries of physics and engineering, delivering chips with transistor densities that would have seemed impossible just a decade ago. Each generation of process technology brings smaller, faster, and more power-efficient chips that drive the next wave of technological innovation.
