Chip Beat

Diagram illustrating the configurable xSPI memory controller IP core's connection to various serial memory devices.

CAST's xSPI IP Core: Real-World Memory Control for Safety-Critical Systems

Embedded systems designers are no longer shackled by the messy fragmentation of serial memory protocols. CAST's new IP core aims to unify and secure these critical interfaces.

5 min read 1 week, 3 days ago

Illustration of interconnected circuit board pathways with RISC-V and HighTec/SiFive logos.

Chip Design & Architecture

RISC-V Ascends: HighTec & SiFive Forge Safety's Future

The automotive and industrial worlds are finally waking up to the transformative power of RISC-V, and two key players just forged a critical alliance. HighTec and SiFive are merging their expertise to accelerate the creation of safe, secure, and high-performance systems built on the open RISC-V architecture.

5 min read 2 weeks, 1 day ago

#automotive

CAST's xSPI IP Core: Real-World Memory Control for Safety-Critical Systems

RISC-V Ascends: HighTec & SiFive Forge Safety's Future